As microprocessor frequencies increase, it becomes necessary to deskew internal and external clocks. It is also desirable to run internal clocks faster than system clock rates. An analog phase-locked loop (PLL) has previously performed this clock generation function; however, as low power applications for microprocessors proliferate, techniques for the implementation of on-chip power management are required. Generally, the implementation of a PLL requires the acquisition of an appropriate frequency and phase using an internal ring oscillator. Analog phase-locked loops typically use a voltage-controlled oscillator (VCO) to generate a period signal that is "locked" to a reference clock signal.
The frequency of the VCO is modulated by an analog voltage adjusted via a feedback mechanism. Typically, the feedback mechanism is supplied from a sequential phase/frequency detector. The sequential phase/frequency detector outputs an "up" or "down" pulse proportional to phase error width and in the direction required to pull in the frequency of the VCO output signal to the target reference clock signal. The output of a sequential phase/frequency detector usually enables a charge pump driving to a loop filter (RC), which in turn controls the frequency of the VCO. The detector outputs can be arbitrarily small, and thus there is usually a dead band associated with such a detector where, for a certain window of time, there is no detectable output. Accordingly, during the dead band ("window width"), the PLL can detect neither "up" nor "down" pulses for a phase/frequency error of a magnitude equal to or less than the window width.
In today's high performance microprocessors, an emphasis is placed on low power operation without compromising the high-performance of the microprocessor. As portable applications proliferate, microprocessor designs incorporate power management techniques to reduce power and extend the battery life of portable computers. One of these techniques entails shutting down the microprocessor while statically maintaining code. This state is called low power stop (LPSTOP), where the microprocessor is completely quiescent, using no power. In portable applications, it is desirable to be able to force microprocessors in and out of the low-power states (LPSTOP) very rapidly. Historically, the largest performance penalty in cycling in and out of LPSTOP has been the amount of time the PLL requires to re-acquire phase lock. Thus, the frequency at which LPSTOP can be used is dictated by how fast a PLL can acquire (re-acquire) phase-lock. Slow lock times reduce the frequency of entering/leaving LPSTOP and result in increased power dissipation. Fast lock times increase the frequency of entering LPSTOP, and reduce power dissipation. Known analog PLL's have long lock times due to the constraints imposed upon the gain.
It is desirable in a PLL to have a frequency detector capable of very fast frequency acquisition which reduces the phase acquisition time penalty, and thereby provides rapid exit from a low-power state. In an all digital phase-locked loop (ADPLL), the VCO is replaced by a digitally-controlled oscillator (DCO). Separation of the frequency acquisition function from the phase acquisition function in the ADPLL enables the performance of each to be individually enhanced, thereby reducing the time penalty of lock acquisition. Accomplishment of this task requires a fast and accurate frequency detector. Known sequential phase/frequency detectors will not suffice since their output pulses may not always be present or may be too narrow to capture. Other known frequency detectors are essentially parallel counters where the reference clock and oscillator clock each increment the counters asynchronously. The output of these counters are compared and if there is a disparity greater than or equal to two, the frequency detector sets a "slow" or "fast" bit accordingly. A disparity of at least two is required since the initial phase error of the clocks (i.e. reference clock and oscillator clock) is unknown and could be any value less than 360 degrees (one cycle). While these frequency detectors work for a coarse resolution, they can take several cycles before a slow/fast decision is made. For high resolution (close frequencies), the approach taken by these frequency detectors requires even more cycles before an accurate frequency comparison can be obtained - essentially amortizing the penalty of a cycle of phase error and a cycle of disparity over all the cycles. Thus, it is desirable to have a frequency detector capable of performing fast and accurate frequency detection.